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wafer CSM series

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 Wafer Level CSP technology, the die ( considered as the package ) are manufactured and tested on the wafer, prior to singulation. This makes it different from all other package types. The size of the package is equal to the size area on the substrate or printed wire board ( PWB ) . Simply, it is Wafer Level packages using solder balls that will interconnect the package to the board. The inter-connection of the solder bump has tremendously driven the technology to a much higher standard: 1) implementation of higher densities on the chip means more I/O;
2) demand for miniaturization and increased functionality in handheld or portable products. The wafer-level package cost is expected to be lower than traditional packages. Since wafer-level package is processed on the wafer, it realizes the same advantages as IC's: the packaging cost for WLP will be reduced as the wafer size increases and/or IC size decreases. Wafer-level packages are ship in standard tape and reel, and assembled by standard SMT technologies. EO CSM-2000 can mark 100% at wafer-level and backside of the wafer without damaging the dies. Chip miniaturization marking is possible with accuracy at 50um. With auto wafer mapping capability, marking on only identified good die is achievable. Also, it is operating in the Windows NT format and is very user friendly. Optional feature on Post Vision Inspection. CSM series can handle 100 ~ 200mm wafer and 300mm wafer. Excellent quality, very high accuracy and yield .